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Generation of Control Signals

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The microprocessor provides RD and WR signal to initiate Read or Write cycle.
Because theses signals are used both for reading/writing memory or reading/writing an input device, it is necessary to generate separate read and write signals for memory and I/O devices.
The 8085 provides IO/M signal to indicate whether the initiated cycle is for I/O devices or for memory device. Using IO/M signal along with RD and WR , it is possible to generate four control signals.

MEMR (Memory Read) : To read data from memory
MEMW (Memory Write) : To write data in memory
IOR (I/O Read) : To read data from I/O devices.
IOW (I/O Write) :To read data in I/O devices.
Generation of Control Signals MEMR,MEMW,IOR,IOW
We know that for OR gate, when the both inputs are low then only output is low.The signal IO/M signal goes low for memeory operation. This signl is logically ORed with RD and WR to get MEMR and MEMW signals. When both RD and IO/M signals go low,MEMR signals is goes low .Simillarly when both WR and ME/MW signal goes low. To generate IO/R and IO/W signals for I/O operation , IO/M signal is first inverted and then logically OR-ed with RD and WR signals.
Truth Table for generating ME/MR, ME/MW, IO/R,IO/W Signals
Same truth table can be implemented using 3:8 decoder.
Bus Drivers
Bus drivers,buses are used to increase the driving capacity of buses.

Uni-directional Buffers:
The address bus is unidirectional buffer,74LS244 is used to buffer higher address bus. It consists of 8-non inverting buffers with try state outputs. Each one can sink 24 mA and source 15 mA of current. These buffers are divided into two groups. The enabling and disabling of these groups are controlled by 1G and 2G lines.
Logic Diagram of 74LS244
Bi-directional Buffers:
To increase the driving capacity of data bus,bi-directional buffer is used. It consists 16 non-inverting buffers,eight for each direction,with tri-state output. The direction of data flow is controlled by the pin DIR. When DIR is high,the data flow from the bus A to the bus B ,when it is low data flows from B to A. The active low enable signal and the DIR signal are ANDed to activate the bus lines. Each buffer in device can sink 24 mA and 15 mA source of current.
Logic Diagram of 74LS245

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