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To design and implement shift register using basic logic gates.

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  • Serial in serial Out
  • Serial in parallel out
  • Parallel in serial out
  • Parallel in parallel out
Apparatus required:-
The following electronics components are required.
·OR Gate (IC-7432)
·D Flip-Flop (IC-7474)
· Digital IC Trainer KIT
·Connecting wires
Description:-
A register is capable of shifting its binary information in one or both directions is known as shift register. The logical configuration of shift register consist of a D-Flip flop cascaded with output of one flip flop connected to input of next flip flop. All flip flops receive common clock pulses which causes the shift in the output of the flip flop. The simplest possible shift register is one that uses only flip flop. The output of a given flip flop is connected to the input of next flip flop of the register. Each clock pulse shifts the content of register one bit position to right.
Pin Diagram of IC-7474:-
Logic Diagram Serial in Parallel Out:-
Truth Table for SISO:-

CLK
Serial in
Serial out
1
1
0
2
0
0
3
0
0
4
1
1
5
X
0
6
X
0
7
X
1
Logic Diagram Serial in Parallel Out:-
Truth- Table for SIPO:-


CLK

DATA
OUTPUT
QA
QB
QC
QD
1
1
1
0
0
0
2
0
0
1
0
0
3
0
0
0
1
1
4
1
1
0
0
1
Logic Diagram Parallel in Serial Out:-
 Truth-Table for Parallel in Serial Out:-
Logic Diagram Parallel in Parallel Out:-
Truth-Table for PIPO:-


CLK
DATA INPUT
OUTPUT
DA
DB
DC
DD
QA
QB
QC
QD
1
1
0
0
1
1
0
0
1
2
1
0
1
0
1
0
1
0

Procedure to Perform:-
Serial in Parallel Out (SIPO):-
  • Connections are made as per circuit diagram.
  • Apply the data at serial I/p
  • Apply one clock pulse at clock 1 (Right Shift) observe this data at QA.
  • Apply the next data at serial I/p.
  • Apply one clock pulse at clock 2, observe that the data on QA will shift to
  • QB and the new data applied will appear at QA.
  • Repeat steps 2 and 3 till all the 4 bits data are entered one by one into the Shift register.
Serial in Serial Out (SISO):-
  • Connections are made as per circuit diagram.
  • Load the shift register with 4 bits of data one by one serially.
  • At the end of 4th clock pulse the first data ‘d0’ appears at QD.
  • Apply another clock pulse; the second data ‘d1’ appears at QD.
  • Apply another clock pulse; the third data appears at QD.
  • Application of next clock pulse will enable the 4th data ‘d3’ to appear at QD. Thus the data applied serially at the input comes out serially at QD
Parallel in Serial Out (PISO):-
  • Connections are made as per circuit diagram.
  • Apply the desired 4 bit data at A, B, C and D.
  • Keeping the mode control M=1 apply one clock pulse. The data applied at
  • A, B, C and D will appear at QA, QB, QC and QD respectively.
  • Now mode control M=0. Apply clock pulses one by one and observe the
  • Data coming out serially at QD
Parallel in Parallel Out (PIPO):-
  • Connections are made as per circuit diagram.
  • Apply the 4 bit data at A, B, C and D.
  • Apply one clock pulse at Clock 2 (Note: Mode control M=1).
  • The 4 bit data at A, B, C and D appears at QA, QB, QC and QD respectively.
Conclusion: - All the output verified the result of Truth Table.
Precaution in lab:-
·All the connections should be tight and proper.
·Handle the ICs carefully.
·Check the connection once again before Switching on the Digital Trainer KIT.
·Switch of the Trainer Kit after performing the Experiment.

1 comment:

  1. you have mentioned mode control m=1 and m=0 in procedure but in circuit design its not there ..please clarify

    ReplyDelete